This invention relates to an image expansion apparatus for two-dimensionally expanding a video signal.
When an image is displayed on a monitor, ordinarily all of the information on a full frame is displayed on the monitor, but there are occasions when it is desired to display part of a frame in expanded form. For example, an area bounded by EFGH on a full frame (the area bounded by ABCD) shown in FIG. 2 can be expanded and displayed as shown in FIG. 3.
In the prior art, an expanded display of this kind is achieved by a circuit arrangement of the type illustrated in FIG. 4. In an apparatus that employs this circuitry, an analog video signal which enters from a terminal 400 is applied to an A/D converter 401 and to a clock generator 402. The latter produces a basic clock, which is necessary to operate the system, from a synchronizing signal contained in the video signal. At the timing of the clock received from the clock generator 402, the A/D converter 401 converts the analog video signal into a digital signal and applies the digital signal to a random-access image memory (RAM) 406. Meanwhile, the same clock signal applied to the A/D converter 401 is sent from the clock generator 402 to a write address generator 403, which produces a write address for the RAM 406. The write address is applied to the RAM 406 via an MPX (multiplexer) 405. The digital data received from the A/D converter 401 is written in the RAM 406 at the address specified by the signal from the write address generator 403.
An ordinary reading operation (namely a reading operation which does not involve expansion or compression) for reading the data written in the ROM 406 is performed as follows: First, a read address produced by a read address generator 404 is applied to the RAM 406 via the MPX 405, whereby the data written in the RAM 406 at this address is read out. The read data is delivered to a D/A converter 407, where it is converted into analog data. The analog data is outputted at a terminal 408. It is assumed here that addresses "01" through "36" as shown in FIG. 5 are assigned to the pixels in the frame shown in FIG. 2. The addresses generated in the ordinary reading operation mentioned above are illustrated in (a) of FIG. 6. The addresses are generated in order from "01" to "36".
An expanded display of the data written in RAM 406 is achieved as follows: Assume that the area EFGH of pixel addresses "15, "16", "17", "21", "23", "27", "28", "29" in FIG. 5 is to be expanded by a factor of 2. In such case, expansion of the display will be possible if the read addresses shown in (b) of FIG. 6 are generated. In this example, each pixel of the area to be enlarged is read out twice in both the main scanning direction and feed scanning direction.
This conventional apparatus for expanding an image involves the following shortcomings:
(1) The apparatus is premised on use of a RAM as a work area for image processing.
(2) Consequently, in order to produce address information to be applied to the RAM, two address generators are required, one which produces addresses for forming a space prior to expansion and one which produces addresses for forming a space after expansion.
(3) When an image signal from, say, a video camera or the like is to be expanded and displayed in real time, use of the RAM necessitates complicated peripheral circuitry for controlling the writing and reading operations of the RAM. This raises cost and enlarges the scale of the circuitry correspondingly.